{ "schema_version": "1.6.1", "id": "RPI-CVE-2026-98869", "modified": "2026-10-22T04:30:02Z", "upstream": [ "CVE-2026-98869" ], "published": "2026-10-21T14:55:19Z", "summary": "bpf: Infer zext_dst based on static register liveness analysis", "details": "In the Linux kernel, the following vulnerability has been resolved:\n\nbpf: Infer zext_dst based on static register liveness analysis\n\nAs reported in the thread [1], the verifier's 32-bit operations zero\nextension logic is broken. This logic is responsible for correct\nsemantics of 32-bit operations on s390 architecture.\n\nAccording to BPF semantics, operation `w1 += 1` is supposed to zero\nextend the upper half of the register `r1`. On s390 the JIT relies on\nthe verifier emitting explicit zero extension before such operations.\n\nThe verifier attempts to minimize the amount of zero extensions\ninserted by tracking whether upper halves of the 64-bit registers are\never used. Previously such tracking worked as follows:\n\n- bpf_reg_state->subreg_def field was set by do_check_insn()\n for each operation defining lower but not the upper halves\n of the register.\n- Whenever an operation reading the whole register was verified,\n the verifier checked register's subreg_def and set\n bpf_insn_aux_data->zext_dst flag as true via a call to\n mark_insn_zext() function.\n- After the verification was complete, a special pass\n bpf_opt_subreg_zext_lo32_rnd_hi32() extended 32-bit operations\n with bpf_insn_aux_data->zext_dst set as true by adding\n explicit zero extension.\n\nNote that the logic above relies on bpf_reg_state->subreg_def,\nwhich is a property of a current verifier state.\nBefore the commit [2] two additional steps happened:\n\n- The verifier tracked upper and lower register halves' liveness as\n flags REG_LIVE_READ{32,64} in bpf_reg_state->live.\n- The function propagate_liveness() called mark_insn_zext()\n in order to transfer the knowledge about which registers have\n their upper halves alive (and thus might require zero extension).\n\nThe commit [2] removed the two steps described above,\nhence making possible a situation like below:\n\n- The register's upper half is set and is used on some verification\n path P1 and the register happens not to be marked as precise.\n- The checkpoint C is created while processing some instruction\n between register initialization and usage.\n- On some other verification path P2 the register's upper half is not\n initialized and that path ends hitting the checkpoint C.\n- In such a case the register's initialization on path P2 would lack\n zext_dst mark, making it possible for the program to inject\n an arbitrary value in the register's upper half.\n\nThis commit replaces subreg_def based logic with computing zext_dst\nstatically, as a part of the bpf_compute_live_registers() analysis:\n\n- The analysis now tracks usage of upper and lower halves of the\n registers separately.\n- If some instruction defines a 32-bit subregister, but not the whole\n register, *and* the upper half of the register is alive after that\n instruction, the instruction is marked as zext_dst.\n\nThere is one notable drop in precision: whenever a BPF subprogram is\ncalled, all 64 bits of parameter registers are presumed to be used.\nThe assumption is that such a drop in precision would not inflict\na noticeable performance penalty.\n\n[1] https://lore.kernel.org/bpf/CAGKGUv=sOuqQtA1Ub-5JXfA4FPosJFYKAQE4B79cK+P1erxqtg@mail.gmail.com/\n[2] commit 107e16979905 (\"bpf: disable and remove registers chain based liveness\")", "affected": [ { "package": { "ecosystem": "Raspberry Pi OS:13", "name": "linux" }, "versions": [ "1:6.18.29-1+rpt1", "1:6.18.33-1+rpt1", "1:6.18.34-1+rpt1", "1:6.18.39-1+rpt1", "1:6.18.50-1+rpt1" ], "ecosystem_specific": { "binaries": [ { "binary_name": "linux-image-6.18.29+rpt-rpi-2712", "binary_version": "1:6.18.29-1+rpt1" }, { "binary_name": "linux-image-6.18.29+rpt-rpi-v6", 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